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ds05-20870-4e fujitsu semiconductor data sheet flash memory cmos 8m (1m 8) bit mbm29lv080a -70/-90/-12 n n n n features ? address specification is not necessary during command sequence ? single 3.0 v read, program and erase minimizes system level power requirements ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 40-pin tsop (i) (package suffix: ptn-normal bend type, ptr-reversed bend type) ? minimum 100,000 program/erase cycles (continued) n n n n product line up n n n n pac k ag e part no. mbm29lv080a ordering part no. v cc = 3.3 v -70 v cc = 3.0 v -90 -12 max. address access time (ns) 70 90 120 max. ce access time (ns) 70 90 120 max. oe access time (ns) 30 35 50 +0.3 v C0.3 v +0.6 v C0.3 v 40-pin plastic tsop (i) (fpt-40p-m06) 40-pin plastic tsop (i) (fpt-40p-m07) marking side marking side
mbm29lv080a -70/-90/-12 2 (continued) ? high performance 70 ns maximum access time ? sector erase architecture 16 sectors of 64k bytes each any combination of sectors can be concurrently erased. also supports full chip erase ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically programs and verifies data at specified address ? data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switches themselves to low power mode ? low v cc write inhibit 2.5 v ? hardware reset pin resets internal state machine to the read mode ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector protection hardware method disables any combination of sectors from program or erase operations ? sector protection set function by extended sector protect command ? temporary sector unprotection temporary sector unprotection via the reset pin * : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29lv080a -70/-90/-12 3 n n n n general description the mbm29lv080a is a 16m-bit, 3.0 v-only flash memory organized as 1m bytes of 8 bits each. the 1m bytes of data is divided into 32 sectors of 64k bytes of flexible erase capability. the 8 bits of data will appear on dq 0 to dq 7 . the mbm29lv080a is offered in a 40-pin tsop (i) package. the device is designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard mbm29lv080a offers access times of 70 ns and 120 ns, allowing operation of high-speed micro- processors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29lv080a is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29lv080a is programmed by executing the program command sequence. this will invoke the embed- ded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margins. any individual sector is typically erased and verified in 1.0 second. (if already preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29lv080a is erased when shipped from the factory. fujitsu has implemented an erase suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a mom-busy sector. thus, true background erase can be achieved. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. the mbm29lv080a also has a hardware reset pin. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. these locations need re-writing after the reset. resetting the device enables the systems microprocessor to read the boot-up firmware from the flash memory. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29lv080a memory electrically erases all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection.
mbm29lv080a -70/-90/-12 4 n n n n flexible sector-erase architecture ? sixteen 64k byte sectors ? loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 15). ? individual-sector or multiple-sector erase capability ? sector protection is user-definable. 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes fffffh effffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 00000h
mbm29lv080a -70/-90/-12 5 n n n n block diagram v ss v cc we ce oe dq 0 to dq 7 reset ry/by buffer state control program voltage generator chip enabl output enable logic time for program/erase erase voltage generator input/output buffers command register low v cc detector ry/by stb stb address latch y-decoder x-decoder y-gating cell matrix a 0 to a 19 data latch
mbm29lv080a -70/-90/-12 6 n n n n connection diagrams a 16 a 15 a 14 a 13 a 12 a 11 a 9 a 8 we reset n.c. ry/by a 18 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 17 v ss n.c. a 19 a 10 dq 7 dq 6 dq 5 dq 4 v cc v cc n.c. dq 3 dq 2 dq 1 dq 0 oe v ss ce a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 18 ry/by n.c. reset we a 8 a 9 a 11 a 12 a 13 a 14 a 15 a 16 a 0 ce v ss oe dq 0 dq 1 dq 2 dq 3 n.c. v cc v cc dq 4 dq 5 dq 6 dq 7 a 10 a 19 n.c. v ss a 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 fpt-40p-m06 tsop (i) (marking side) mbm29lv080a mbm29lv080a (marking side) fpt-40p-m07
mbm29lv080a -70/-90/-12 7 n n n n logic symbol table 2 mbm29lv080a user bus operation legend: l = v il , h = v ih , x = v il or v ih . = pulse input. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. see table 6. 2. we can be v il if oe is v il , oe at v ih initiates the write operations. 3. refer to the section on sector protection. 4. v cc = 3.3 v 10% 5. it is also used for the extended sector protection. operation ce oe we a 0 a 1 a 6 a 9 a 10 dq 0 to dq 7 reset auto-select manufacture code (1) l l h l l l v id l code h auto-select device code (1) l l h h l l v id l code h read (2) l l h a 0 a 1 a 6 a 9 a 10 d out h standby h x x x x x x x high-z h output disable l h h x x x x x high-z h write (program/erase) l h l a 0 a 1 a 6 a 9 a 10 d in h enable sector protection (3), (4) l v id lhlv id xx h verify sector protection (3), (4) l l h l h l v id l code h temporary sector unprotection (5) x x x x x x x x x v id reset (hardware)/standby x x x x x x x x high-z l table 1 mbm29lv080a pin configuration pin function address inputs data inputs/outputs chip enable output enable write enable pin not connected internally ready/busy output device ground device power supply hardware reset pin/ temporary sector unprotection a 0 to a 19 dq 0 to dq 7 ce oe we reset n.c. ry/by v ss v cc 20 a 0 to a 19 we oe ce dq 0 to dq 7 8 reset ry/by
mbm29lv080a -70/-90/-12 8 n n n n functional description read mode the mbm29lv080a has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc - t ce time.) see figure 5.1 for timing specifications. standby mode there are two ways to implement the standby mode on the mbm29lv080a device, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current is consumed is less than 5 m a max. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29lv080a data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to activate this mode, mbm29lv080a automatically switchs itself to low power mode when mbm29lv080a addresses remain stably during access time of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level). standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , a 6 , and a 10 . (see table 3.1.)
mbm29lv080a -70/-90/-12 9 the manufacturer and device codes may also be read via the command register, for instances when the mbm29lv080a is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 6. (refer to autoselect command section.) byte 0 (a 0 = v il ) represents the manufactures code (fujitsu = 04h) and byte 1 (a 0 = v ih ) represents the device identifier code mbm29lv080a = 38h. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see tables 3.1 and 3.2.) in order to determine which sectors are write protected, a 1 must be at v ih while running through the sector addresses; if the selected sector is protected, a logical 1 will be output on dq 0 (dq 0 = 1). table 3.1 mbm29lv080a sector protection verify autoselect code *: outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. table 3.2 expanded autoselect code table type a 16 to a 19 a 10 a 6 a 1 a 0 code (hex) manufactures code x v il v il v il v il 04h device code mbm29lv080a x v il v il v il v ih 38h sector protection sector addresses v il v il v ih v il 01h* type code dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h00000100 device codembm29lv080a38h00111000 sector protection 01h00000001
mbm29lv080a -70/-90/-12 10 table 4 sector address tables sector address a 19 a 18 a 17 a 16 address range sa000000 0000h to 0ffffh sa100011 0000h to 1ffffh sa200102 0000h to 2ffffh sa300113 0000h to 3ffffh sa401004 0000h to 4ffffh sa501015 0000h to 5ffffh sa601106 0000h to 6ffffh sa701117 0000h to 7ffffh sa810008 0000h to 8ffffh sa910019 0000h to 9ffffh sa101010a 0000h to affffh sa111011b 0000h to bffffh sa121100c 0000h to cffffh sa131101d 0000h to dffffh sa141110e 0000h to effffh sa151111f 0000h to fffffh
mbm29lv080a -70/-90/-12 11 write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the mbm29lv080a features hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 15). the sector protection feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il , a 0 = a 6 = v il , and a 1 = v ih . the sector addresses (a 19 , a 18 , a 17 ,and a 16 ) should be set to the sector to be protected. tables 4 and 5 define the sector address for each of the sixteen (16) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see figures 13 and 21 for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 19 , a 18 , a 17 ,and a 16 ) while (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the devices will read 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , a 6 , and a 10 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 19 , a 18 , a 17 ,and a 16 ). are the sector address will produce a logical 1 at dq 0 for a protected sector. see tables 3.1 and 3.2 for autoselect codes. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the mbm29lv080a device in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously protected sectors will be protected again. see figure 15 and 22.
mbm29lv080a -70/-90/-12 12 table 5 mbm29lv080a standard command definitions notes: 1. address bit = x = h or l. 2. bus operations are defined in table 2. 3. ra=address of the memory location to be read. pa=address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa=address of the sector to be erased. the combination of a 19 , a 18 , a 17 , and a 16 will uniquely select any sector. 4. rd=data read from location ra during read operation. pd=data to be programmed at location pa. data is latched on the rising edge of we . 5. both read/reset commands are functionally equivalent, resetting the device to the read mode. command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the devices to read mode. table 6 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover, both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 0 to dq 7 bits are ignored. command sequence (notes 1, 2, 3) bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data read/reset (note 5) 1 xxxh f0h read/reset (note 5) 3 xxxh aah xxxh 55h xxxh f0h ra rd autoselect 3 xxxh aah xxxh 55h xxxh 90h byte program (notes 3, 4) 4 xxxh aah xxxh 55h xxxh a0h pa pd chip erase 6 xxxh aah xxxh 55h xxxh 80h xxxh aah xxxh 55h xxxh 10h sector erase (note 3) 6 xxxh aah xxxh 55h xxxh 80h xxxh aah xxxh 55h sa 30h sector erase suspend 1 xxxh b0h sector erase resume 1 xxxh 30h
mbm29lv080a -70/-90/-12 13 table 6 mbm29lv080a extended command definitions spa:sector address to be protected. set sector address (sa) and (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0). sd: sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. *1: this command is valid while fast mode. *2: this command is valid while reset =v id . *3: the data "00h" is also acceptable. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read character- istics and waveforms for the specific timing parameters.(see figures 5.1 and 5.2.) autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. fol- lowing the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address x001h returns the device code (mbm29lv080a = 38h). (see tables 3.1 and 3.2.) all manufacturer and device codes will exhibit odd parity with the msb (dq 7 ) defined as the parity bit. sector state (protection or unprotection) will be informed address x0002h. scanning the sector addresses (a 19 , a 18 , a 17 , a 16 ) while (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be perform margin mode on the protected sector. (see table 2.) to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command se- quence. command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read cycle addr data addr data addr data addr data fast mode set 3 xxxh aah xxxh 55h xxxh 20h fast program * 1 2 xxxh a0h pa pd fast mode reset * 1 2 xxxh 90h xxxh f0h * 3 extended sector protection * 2 4 xxxh 60h spa 60h spa 40h spa sd
mbm29lv080a -70/-90/-12 14 byte programming the device is programmed on a byte-by-byte basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. (see table 8, hardware sequence flags.) therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occurs during the pro- gramming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device (exceed timing limits), or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 17 illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. figure 18 illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . after time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on table 6. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 s, otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 50 s time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. resetting the devices once execution has begun will corrupt the data in that sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section
mbm29lv080a -70/-90/-12 15 for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 15). sector erase does not require the user to program the devices prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 50 s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector program time (preprogramming) + sector erase time] number of sector erase. figure 18 illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or program to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume commands. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 20 m s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 , or the toggle bit (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing.
mbm29lv080a -70/-90/-12 16 extended command (1) fast mode mbm29lv080a has fast mode function. this mode dispenses with the initial two unlock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in normal command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. (refer to the figure 23 extended algorithm.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program setup command (a0h) and data write cycles (pa/pd). (refer to the figure 23 extended algorithm.) (3) extended sector protection in addition to normal sector protection, the mbm29lv080a has extended sector protection as extended function. this function enable to protect sector by forcing v id on reset pin and write a command sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition, the operation is initated by writing the setup command (60h) into the command register. then, the sector addresses pins (a 19 , a 18 , a 17 , and a 16 ) and (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins), and write extended sector protect command (60h). a sector is typically protected in 250 m s. to verify programming of the protection cicuitry, the sector addresses pins (a 19 , a 18 , a 17 , and a 16 ) and (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector protect command (60h) again. to terminate the opetation, it is necessary to set reset pin to v ih .
mbm29lv080a -70/-90/-12 17 write operation status table 7 hardware sequence flags notes: 1. performing successive read operations from any address will cause dq 6 to toggle. 2. reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. 3. dq 0 and dq 1 are reserve pins for future use. 4. dq 4 is fujitsu internal use only. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded/erase algorithm 0 toggle 0 1 toggle erase suspend mode erase suspend read erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle (note 1) 00 1 (note 2) exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded/erase algorithm 0 toggle 1 1 n/a erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29lv080a -70/-90/-12 18 dq 7 data polling the mbm29lv080a device features data polling as a method to indicate to the host that the embedded algo- rithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in figure 19. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29lv080a data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algo- rithm, or sector erase time-out. (see table 8.) see figure 9 for the data polling timing specifications and diagrams. dq 6 toggle bit i the mbm29lv080a also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 s and then stop toggling without the data having changed. in erase, the device will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 50 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. see figure 10 and figure 20 for the toggle bit i timing specifications and diagrams.
mbm29lv080a -70/-90/-12 19 dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling dq 7 , dq 6 is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in table 2. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1 please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see table 8: hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. for example, dq 2 and dq 6 can be used together to determine the erase-suspend-read mode. (dq 2 toggles while dq 6 does not.) see also above table 9 and figure 16. furthermore, dq 2 can also be used to determine which sector is being erased. when the devices are in the erase mode, dq 2 toggles if this bit is read from the erasing sector.
mbm29lv080a -70/-90/-12 20 table 8 toggle bit status notes: 1. performing successive read operations from any address will cause dq 6 to toggle. 2. reading the address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. ry/by ready/busy pin the mbm29lv080a provides a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the device will not accept any additional program or erase commands with the exception of the erase suspend command. if the mbm29lv080a is placed in an erase suspend mode, the ry/by output will be high, by means of connecting with a pull up resistor to v cc . during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. see figure 11 and 12 for a detailed timing diagram. the ry/by pin is pulled high in stadby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . reset hardware reset pin the mbm29lv080a device may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the devices requires an additional t rh before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see figure 12 for the timing diagram. refer to tem- porary sector unprotection for additional functionality. if hardware reset occurs during embedded erase algorithm, there is a possibility that the erasing sector(s) cannot be used. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle erase-suspend read (erase-suspended sector) (note 1) 11toggle erase-suspend program dq 7 toggle (note 1) 1 (note 2)
mbm29lv080a -70/-90/-12 21 data protection the mbm29lv080a is designed to offer protection against accidental erasure or programming caused by spu- rious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporates several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 2.3 v (typically 2.4 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 2.3 v. if embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
mbm29lv080a -70/-90/-12 22 n n n n absolute maximum ratings notes: 1. minimum dc voltage on input or l/o pins is - 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or l/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 , oe and reset pins is -0.5 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed 9.0 v. maximum dc input voltage on a 9 , oe and reset pins is +13.0 v which may overshoot to 14.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating ranges operating ranges define those limits between which the functionality of the device is quaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol conditions rating unit min. max. storage temperature tstg ? C55 +125 c ambient temperature with power applied t a ? C40 +85 c voltage with respect to ground all pins except a 9 , oe , reset (note 1) v in , v out ? C0.5 v cc +0.5 v power supply voltage (note 1) v cc ? C0.5 +5.5 v a 9 , oe , and reset (note 2) v in ? C0.5 +13.0 v parameter symbol conditions value unit min. max. ambient temperature t a ? C40 +85 c power supply voltage v cc mbm29dl16xte/be-70 +3.0 +3.6 v mbm29dl16xte/be-90/12 +2.7 +3.6 v
mbm29lv080a -70/-90/-12 23 n n n n maximum overshoot / undershoot + 0.6 v - 0.5 v 20 ns - 2.0 v 20 ns 20 ns figure 1 maximum undershoot waveform v cc + 0.5 v + 2.0 v v cc + 2.0 v 20 ns 20 ns 20 ns figure 2 maximum overshoot waveform 1 + 13.0 v v cc + 0.5 v + 14.0 v 20 ns 20 ns 20 ns figure 3 maximum overshoot waveform 2 note : this waveform is applied for a 9 , oe and reset .
mbm29lv080a -70/-90/-12 24 n n n n dc characteristics notes: 1. the l cc current listed includes both the dc operating current and the frequency dependent component. 2. l cc active while embedded erase or embedded program is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. this voltage is for sector protection operation. 5. (v id - v cc ) do not exceed 9 v. parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max. C1.0 +1.0 a i lo output leakage current v out = v ss to v cc , v cc = v cc max. C1.0 +1.0 a i lit a 9 , oe , reset inputs leakage current v cc = v cc max., a 9 , oe , reset = 12.5 v 35a i cc1 v cc active current (note 1) ce = v il , oe = v ih , f = 10 mhz 22 ma ce = v il , oe = v ih , f = 5 mhz 12 ma i cc2 v cc active current (note 2) ce = v il , oe = v ih 35ma i cc3 v cc current (standby) v cc = v cc max., ce = v cc 0.3 v, reset = v cc 0.3 v 5a i cc4 v cc current during reset (standby, reset ) v cc = v cc max., reset = v ss 0.3 v 5a i cc5 v cc current (automatic sleep mode) (note 3) v cc = v cc max., reset = v cc 0.3 v, ce = v ss 0.3 v, v in = v cc 0.3 v or v ss 0.3 v 5a v il input low level C0.5 0.6 v v ih input high level 2.0 v cc + 0.3 v v id voltage for autoselect, sector protection and temporary sector unprotection (a 9 , oe , reset ) (note 4, 5) 11.512.5v v ol output low voltage level i ol = 4.0 ma, v cc = v cc min. 0.45 v v oh1 output high voltage level i oh = C2.0 ma, v cc = v cc min. 2.4 v v oh2 i oh = C100 a v cc C 0.4 v v lko low v cc lock-out voltage 2.3 2.5 v
mbm29lv080a -70/-90/-12 25 n n n n ac characteristics ? read only operations characteristics note: test conditions: output load: 1 ttl gate and 30 pf (mbm29lv080a-70) 1 ttl gate and 100 pf (mbm29lv080a-90/-12) input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbols description test setup -70 (note) -90 (note) -12 (note) unit jedec standard t avav t rc read cycle time min. 70 90 120 ns t avqv t acc address to output delay ce = v il oe = v il max. 70 90 120 ns t elqv t ce chip enable to output delay oe = v il max. 70 90 120 ns t glqv t oe output enable to output delay max. 30 35 50 ns t ehqz t df chip enable to output high-z max. 25 30 30 ns t ghqz t df output enable to output high-z max. 25 30 30 ns t axqx t oh output hold time from address, ce or oe , whichever occurs first min. 0 0 0 ns t ready reset pin low to read mode max. 20 20 20 m s c l 3.3 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w figure 4 test conditions notes: c l = 30 pf including jig capacitance (mbm29lv080a-70) c l = 100 pf including jig capacitance (mbm29lv080a-90/-12)
mbm29lv080a -70/-90/-12 26 ? write (erase/program) operations (continued) parameter symbols description mbm29lv080a unit jedec standard -70 -90 -12 t avav t wc write cycle time min. 70 90 120 ns t avwl t as address setup time min. 0 0 0 ns t wlax t ah address hold time min. 45 45 50 ns t dvwh t ds data setup time min. 35 45 50 ns t whdx t dh data hold time min. 0 0 0 ns t oes output enable setup time min. 0 0 0 ns t oeh output enable hold time read min. 0 0 0 ns toggle and data polling min. 10 10 10 ns t ghwl t ghwl read recover time before write (oe high to we low) min. 0 0 0 ns t ghel t ghel read recover time before write (oe high to ce low) min. 0 0 0 ns t elwl t cs ce setup time min. 0 0 0 ns t wlel t ws we setup time min. 0 0 0 ns t wheh t ch ce hold time min. 0 0 0 ns t ehwh t wh we hold time min. 0 0 0 ns t wlwh t wp write pulse width min. 35 45 50 ns t eleh t cp ce pulse width min. 35 45 50 ns t whwl t wph write pulse width high min. 25 25 30 ns t ehel t cph ce pulse width high min. 25 25 30 ns t whwh1 t whwh1 programming operation typ. 8 8 8 s t whwh2 t whwh2 sector erase operation (note 1) typ. 1 1 1 s t eoe delay time from embedded output enable max. 30 35 50 ns t vcs v cc setup time min. 50 50 50 s t vlht voltage transition time (note 2) min. 4 4 4 s t wpp write pulse width (note 2) min. 100 100 100 s t oesp oe setup time to we active (note 2) min. 4 4 4 s t csp ce setup time to we active (note 2) min. 4 4 4 s t rb recover time from ry/by min. 0 0 0 ns t rh reset hold time before read min. 200 200 200 ns
mbm29lv080a -70/-90/-12 27 (continued) notes: 1. this does not include the preprogramming time. 2. this timing is for sector protection operation. parameter symbols description mbm29lv080a unit jedec standard -70 -90 -12 t busy program/erase valid to ry/by delay max. 90 90 90 ns t vidr rise time to v id (note 2) min. 500 500 500 ns t rp reset pulse width min. 500 500 500 ns
mbm29lv080a -70/-90/-12 28 n n n n switching waveforms ? key to switching waveforms we oe ce t acc t df t ce t oe outputs t rc addresses addresses stable high-z output valid high-z t oeh t oh figure 5.1 ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h h or l: any change permitted does not apply will be steady will be change from h to l will be change from l to h changing, state unknown center line is high- impedance off state
mbm29lv080a -70/-90/-12 29 reset t acc t oh outputs t rc addresses addresses stable high-z output valid t rh figure 5.2 ac waveforms for hardware reset/read operations
mbm29lv080a -70/-90/-12 30 t ch t wp t whwh1 t wc t ah ce oe t rc addresses data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we xxxh pa pa t oh t df data polling 3rd bus cycle t cs t ce t ds d out notes: pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. figure 6 ac waveforms for alternate we controlled program operations
mbm29lv080a -70/-90/-12 31 t cp t ds t whwh1 t wc t ah we oe addresses data t as t cph t dh dq 7 a0h d out ce xxxh pa pa data polling 3rd bus cycle t ws t wh t ghel pd figure 7 ac waveforms for alternate ce controlled program operations notes: pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence.
mbm29lv080a -70/-90/-12 32 v cc ce oe addresses data t wp we xxxh xxxh xxxh xxxh xxxh sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc 55h 55h 80h aah aah 10h 30h for sector erase figure 8 ac waveforms for chip/sector erase operations *: sa is the sector address for sector erase. addresses = xxxh for chip erase.
mbm29lv080a -70/-90/-12 33 figure 9 ac waveforms for data polling during embedded algorithm operations *: dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe t whwh1 or 2 ce oe we data t df t ch t ce high-z dq 7 = valid data dq 7 * dq 7 t eoe high-z dq 0 to dq 6 valid data dq 0 to dq 6 data dq 0 to dq 6 = output flag t oeh ce we oe dq 6 t oe t oes t oeh t dh * data dq 6 = toggle dq 6 = toggle dq 6 = stop toggling dq 0 to dq 7 data valid figure 10 ac waveforms for toggle bit i during embedded algorithm operations *: dq 6 stops toggling. (the device has completed the embedded operation.)
mbm29lv080a -70/-90/-12 34 the rising edge of the last we signal ce ry/by we t busy entire programming or erase operations figure 11 ry/by timing diagram during program/erase operations t rp reset t ready ry/by we t rb figure 12 reset , ry/by timing diagram
mbm29lv080a -70/-90/-12 35 t vlht sax a 19 , a 18 a 17 , a 16 say a 0 a 6 , a 10 a 9 3 v t vlht oe 3 v t vlht t vlht t oesp t wpp t csp we ce t oe 01h data v cc a 1 t vlht 12 v 12 figure 13 ac waveforms for sector protection timing diagram sax: sector address for initial sector say : sector address for next sector
mbm29lv080a -70/-90/-12 36 spay reset a 6 , a 10 oe we ce data a 1 v cc a 0 add spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe figure 14 extended sector protection timing diagram spax: sector address to be protected spay : next sector address to be protected time-out : time-out window = 250 m s (min.)
mbm29lv080a -70/-90/-12 37 3 v reset v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vidr v id t vlht unprotection period figure 15 temporary sector unprotection timing diagram dq 2 dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe figure 16 dq 2 vs. dq 6 note: dq 2 is read from the erase-suspended sector.
mbm29lv080a -70/-90/-12 38 n n n n flow chart figure 17 embedded program tm algorithm embedded algorithm no yes yes program command sequence (address/command): xxxh/aah xxxh/55h xxxh/a0h write program command sequence (see below) data polling increment address last address ? verify data ? program address/program data start programming completed embeded program algorithm in progress no
mbm29lv080a -70/-90/-12 39 xxxh/aah xxxh/55h xxxh/aah xxxh/80h xxxh/10h xxxh/55h xxxh/aah xxxh/55h xxxh/aah xxxh/80h xxxh/55h additional sector erase commands are optional. write erase command sequence (see below) data polling chip erase command sequence (address/command): individual sector/multiple sector erase command sequence (address/command): sector address/30h sector address/30h sector address/30h erasure completed start no yes data = ffh ? embeded program algorithm in progress figure 18 embedded erase tm algorithm embedded algorithm
mbm29lv080a -70/-90/-12 40 dq 7 = data? * no no dq 7 = data? dq 5 = 1? yes yes no read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va yes start fail pass figure 19 data polling algorithm *: dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation.
mbm29lv080a -70/-90/-12 41 start yes no toggle bit = toggle ? dq 5 = 1? yes no no yes read dq 7 to dq 0 read dq 7 to dq 0 read dq 7 to dq 0 twice toggle bit = toggle ? *1 *1, *2 program/erase operation not complete. write reset command program/erase operation complete. figure 20 toggle bit algorithm *1: reset toggle bit twice to determine whether or not it is toggle. *2: recheck toggle bit because it may stop toggle as dq 5 changes to 1.
mbm29lv080a -70/-90/-12 42 setup sector addr. (a 19 , a 18 , a 17 , a 16 ) activate we pulse yes yes no no oe = v id , a 9 = v id , a 6 = ce = v il , reset = v ih a 0 = v il , a 1 = v ih plscnt = 1 time out 100 m s read from sector (a 1 = v ih , a 0 = v il , addr. = sa, a 6 = v il ) remove v id from a 9 write reset command increment plscnt no yes protect another sector? data = 01h? plscnt = 25? remove v id from a 9 write reset command start sector protection completed we = v ih , ce = oe = v il (a 9 should remain v id ) device failed figure 21 sector protection algorithm
mbm29lv080a -70/-90/-12 43 reset = v id *1 perform erase or program operations reset = v ih start temporary sector unprotection completed *2 figure 22 temporary sector unprotection algorithm *1: all protected sectors are unprotected. *2: all previously protected sectors are protected once again.
mbm29lv080a -70/-90/-12 44 device failed plscnt = 25 ? yes yes yes no no plscnt = 1 data = 01h? protect other sector ? sector protection completed wait to 250 m s reset = v id start wait to 4 m s to setup sector protection write xxxh/60h extended sector protection entry? no yes no read from sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) to verify sector protection write 40h to sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) to sector protection write 60h to sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) device is operating in temporary secto unprotection mode remove v id from reset write reset command remove v id from reset write reset command setup next sector address increment plscnt figure 23 extended sector protection algorithm
mbm29lv080a -70/-90/-12 45 no no yes yes xxxh/20h xxxh/a0h verify data? xxxh/90h xxxh/f0h programming completed last address ? data polling device xxxh/55h set fast mode in fast program reset fast mode xxxh/aah start program address/program data increment address fast mode algorithm figure 24 embedded program tm algorithm for fast mode
mbm29lv080a -70/-90/-12 46 n n n n erase and programming performance n n n n tsop (i) pin capacitance note: test conditions t a = 25c, f = 1.0 mhz parameter limits unit comments min. typ. max. sector erase time 1 10 s excludes programming time prior to erasure byte programming time 8 300 s excludes system-level overhead chip programming time 8.4 25 s excludes system-level overhead erase/program cycle 100,000 cycle parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 7 10 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 10 12.5 pf
mbm29lv080a -70/-90/-12 47 n n n n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29lv080 a -70 ptn pa c k a g e t y p e ptn = 40-pin thin small outline package (tsop (i)) standard pinout ptr = 40-pin thin small outline package (tsop (i)) reverse pinout speed option see product selector guide device revision device number/description mbm29lv080 8mega-bit (1m 8-bit) cmos flash memory 3.0 v-only read, program, and erase part number package remarks mbm29lv080a-70ptv mbm29lv080a-90ptv mbm29lv080a-12ptv 40-pin plastic tsop(i) (fpt-40p-m06) standard pinout mbm29lv080a-70ptr mbm29lv080a-90ptr MBM29LV080A-12PTR 40-pin plastic tsop(i) (fpt-40p-m07) reverse pinout
mbm29lv080a -70/-90/-12 48 n n n n package dimensions c 1994 fujitsu limited f40007s-1c-1 1 40 20 21 index "a" lead no. 20.00?.20 (.787?008) 18.40?.20 (.724?008) 19.00?.20 (.748?008) 0.10(.004) 0.50?.10 (.020?004) 0.15?.05 (.006?002) 0.20?.10 (.008?004) 9.50(.374) ref. m 0.10(.004) 0.50(.0197) typ 10.00?.20 (.394?008) 0.05(.002)min (stand off) .043 ?002 +.004 ?.05 +0.10 1.10 details of "a" part max 0.35(.014) max 0.15(.006) 0.15(.006) 0.25(.010) (mounting height) dimensions in mm (inches). 40-pin plastic tsop(i) (fpt-40p-m06) c 1994 fujitsu limited f40008s-1c-1 1 40 20 21 index "a" lead no. 19.00?.20 (.748?008) 0.10(.004) 20.00?.20 (.787?008) 18.40?.20 (.724?008) 0.15?.05 (.006?002) 0.50?.10 (.020?004) 10.00?.20 (.394?008) 9.50(.374) ref. 0.20?.10 (.008?004) 0.50(.0197) typ m 0.10(.004) 0.05(.002)min (stand off) .043 ?002 +.004 ?.05 +0.10 1.10 0.25(.010) 0.15(.006) 0.15(.006) max 0.35(.014) max details of "a" part (mounting height) dimensions in mm (inches). 40-pin plastic tsop(i) (fpt-40p-m07)
mbm29lv080a -70/-90/-12 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0008 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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